An SPI timing diagram is a picture of one transfer: chip-select, clock, and the bits on MOSI and MISO. This page is the mode table and the timing names. A fully drawn mode-0 frame, with every bit labeled, is on the examples page.
Understanding SPI Timing Diagrams
The Serial Peripheral Interface (SPI) is one of the most widely used communication protocols in embedded systems. SPI timing diagrams show how the clock, data, and chip select signals interact during data transfer.
Key SPI Signals
- SCLK (Serial Clock) – The clock signal generated by the master device
- MOSI (Master Out Slave In) – Data transmitted from master to slave
- MISO (Master In Slave Out) – Data transmitted from slave to master
- CS/SS (Chip Select) – Active-low signal to select the target slave
SPI Modes and Clock Polarity
SPI operates in four modes defined by Clock Polarity (CPOL) and Clock Phase (CPHA):
| Mode | CPOL | CPHA | Description |
|---|---|---|---|
| 0 | 0 | 0 | Clock idle low, data sampled on rising edge |
| 1 | 0 | 1 | Clock idle low, data sampled on falling edge |
| 2 | 1 | 0 | Clock idle high, data sampled on falling edge |
| 3 | 1 | 1 | Clock idle high, data sampled on rising edge |
How to read a mode-0 frame
Pull CS low, then count rising edges of SCLK. The MOSI level before each rising edge is the next bit the peripheral latches. MISO is the bit the master latches on that same edge. Eight edges move one byte each way. CS high ends the frame. The worked figure uses MOSI = 0xA5 and MISO = 0x3C.
To draw it, open the editor and add four bit rows. The handbook covers paint, arrows, and PNG or SVG export.
SPI Timing Parameters
Datasheets attach numbers to a small set of intervals. The drawing shows where each interval sits. The number comes from the chip, not from the editor:
- tSETUP – Data setup time before clock edge
- tHOLD – Data hold time after clock edge
- tCLK – Clock period
- tCSS – Chip select setup time
- tCSH – Chip select hold time
Related: worked SPI, I2C, and UART frames · I2C timing · open the editor